Abstract: For different engineering applications, neural networks varied in scale, topology, transfer functions and learning algorithms. A reconfigurable approach for neural hardware implementation was proposed, which was not only flexible to meet those changes, also with the fast prototyping ability for market requirements. Three kinds of reconfigurable processing units were presented based on the analysis of neural network's reeonfiguration. A reconfigurable systolic architecture was put forward and the method of mapping BP networks into this architecture was introduced. Implementation issues were discussed with an example. The results showed that a high learning speed of 432 M CUPS(Connections Updated Per Second)was achieved (working at 100 MHz using 22 multipliers) at a reasonable cost.